1. Field of the Invention
This present invention relates to a Pipelined Analog-to-Digital Converter, especially to a Pipelined Analog-to-Digital Converter comprising two different stage circuits. These two stage circuits have different converting rates.
2. Description of the Prior Art
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a configuration schematic diagram of a conventional Pipelined Analog-to-Digital Converter. FIG. 2 is a schematic diagram of the working time sequence of a stage circuit in a conventional Pipelined Analog-to-Digital Converter. A conventional pipelined analog-to-digital converter 10 comprises a plurality of stage circuits Si (i=1xcx9cn), a register 15 and a digital output code integrating device 17. Each conventional stage circuit Si comprises a sample-and-hold 12, a comparator 14, an amplifier 16 and a compensation filament 18. The process that the conventional stage circuits Si converts an analog input signal to a digital data output can be divided into two modes which are the sampling mode and the amplifying mode.
The principle of how the pipelined analog-to-digital converter 10 work is as below: when an outside analog signal Vin is input into the first stage circuit S1 of the Pipelined Analog-to-Digital Converter 10, the first stage circuit S1 first enters the sampling mode. That is, the sample-and-hold 12 samples and holds the analog signal Vin, and then compares the analog signal Vin with a reference signal Vref set in advance in the comparator 14 to acquire a digital output code. After finishing these actions, enter the amplifying mode. In the amplifying mode, the amplifier 16 amplifies the analog signal Vin. Then according to the digital output code acquired by the comparator 14, the compensation filament 18 increases a compensation value to the amplified analog signal, and transmits the amplified analog signal to the second stage circuit S2.
Later stage circuits repeat the actions aforesaid, but the last stage circuit Sn without amplifying, only proceeds the sampling mode and the level judgment. The digital output codes output by each of the stage circuits will temporarily store in the register 15. When the last stage circuit Sn outputs a digital output code, a digital output code integrating device 17 integrates all the digital output codes to get a digital data Bout corresponding to the analog signal Vin.
Wherein, the resolution k of each stage circuit is decided by the number of the reference signal of the comparator. If the resolution of each stage is one bit, the reference signal is usually xc2x1Vref/4. When the resolution of a stage circuit is determined, the amplified multiple G of the amplifier of the stage circuit will also be determined. The relation is G=2k.
Because each stage circuit comprises a sample-and-hold 12, each stage circuit can work at the same time. For example, when a second stage circuit outputs an analog signal to a third stage circuit, the second stage starts to deal with the analog signal in the sample-and-hold input by the first stage circuit. Therefore, except the latency in the very beginning, the pipelined analog-to-digital converter resembles a flash analog-to-digital converter, which can output a convert outcome in every clock period.
If the configuration of the resolution in each stage circuit is 1 bit, a shortcoming of the pipeline analog-to-digital converter is that a lot of stage circuits are necessary, so that the number of amplifiers needs to increase. A ten bits pipeline analog-to-digital converter has to adopt nine stages. Therefore, need nineteen comparators and eight amplifiers. The more amplifiers, the more power wasted. However, if improve the resolution of stages, the power required in the amplifier and the comparator of each stage circuit has to increase, and the power totally wasted by the pipeline analog-to-digital converter cannot be decreased greatly, either. Therefore, a new stage circuit configuration is necessary to effectively decrease the power totally wasted by the pipeline analog-to-digital converter.
U.S. Pat. No. 6,195,032 is for solving this phenomenon. The patent uses a recycle method to combine two stage circuits as a block in which signals repeat converting, in order to improve that one stage circuit only performs one calculation for an analog signal. That is, after converted by two stage circuits in one block, the analog signal is not output to the next stage circuit, but is repeated converting several times inside the block. Thereby, a configuration, which originally needs N stage circuits, now can decrease to need only two stage circuits to repeat calculating. Or combine several blocks, so that the analog signal can be repeated calculating in one block several times to meet the purpose to decrease the number of stage circuits. However, when applying the method of U.S. Pat. No. 6,195,032, it is necessary to raise the converting rate of a stage circuit more than one time. Therefore, although applying U.S. Pat. No. 6,195,032 can decrease the area occupied and the latency caused by the converter, it can also let the requirement of the unit gain bandwidth of the amplifier in the stage circuit be raised more than one time. This phenomenon will cause the pipeline analog-to-digital converter, which applies U.S. Pat. No. 6,195,032 cannot be applied in high rate calculating.
An objective of the invention is to provide a pipeline analog-to-digital converter to solve the problem of the prior art.
Another objective of the invention is to provide a pipeline analog-to-digital converter with fewer elements, which can effectively decrease the number of amplifiers to obviously decrease the power totally wasted by the converter.
Another objective of the invention is to provide a pipeline analog-to-digital converter, which decreases the stage circuits; therefore the area occupied by the whole converter can be reduced.
This invention relates to a pipeline analog-to-digital converter for converting a first analog signal to a digital data. The converter comprises a group of first stage circuits, a group of second stage circuits, a third stage circuit and a digital output code integrating device.
The group of first stage circuits converts the first analog signal to at least one digital output code, and outputs a second analog signal. The group of first stage circuits comprises at least one first stage circuit. Each of the first stage circuits has a first converting rate, in order to convert the analog signal inputted into the first stage circuit to a digital output code in one clock.
The group of second stage circuits series- connects after said group of first stage circuits. The group of second stage circuits converts the second analog signal to at least two digital output codes, and generates a third analog signal. The group of second stage circuits comprises at least one second stage circuit. Each of the second stage circuits has a second converting rate which is higher than the first converting rate, so as to output at least two digital output codes per clock.
The third stage circuit series connects after the group of second stage circuits, used for converting the third analog signal to at least one digital output code. The digital output code integrating device integrates the digital output codes converted by the group of first stage circuits, the group of second stage circuits, and the third stage circuit to generate the digital data.
Thereby, the stage circuits in the back of the pipeline analog-to-digital converter have a higher converting rate, which can convert the analog signal to more than two digital output codes in one clock. Therefore, in contrast to a conventional pipeline analog-to-digital converter with the same resolution, the pipeline analog-to-digital converter of the present invention can reduce the number of the stage circuits needed, and further reduce the area occupied by the whole converter. The pipeline analog-to-digital converter of this invention increases only the converting rate of the back stage circuit; therefore the requirement of the elements of the back stage circuit will not be higher than the front circuit. Thus the pipeline analog-to-digital converter of the present invention could meet the demand of high rate application.
The advantage and spirit of the invention may be understood by the following recitations together with the appended drawings.